Binary translation in computers refers to the emulation of one instruction set by another through translation of assembly level code or instructions. Sequences of instructions are translated from the source instruction set to the target instruction set. Static binary translation aims to convert all of the code of an executable file into code that runs on the target architecture without having to run the code first, as is done in dynamic binary translation. This is very difficult to do correctly, since not all the code can be discovered by the translator. For example, some parts of the executable may be reachable only through indirect branches, whose value is known only at run-time.
Dynamic binary translation looks at a short sequence of code—typically on the order of a single basic block—then translates it and caches the resulting sequence. Code is only translated as it is discovered and when possible branch instructions are made to point to already translated and saved code. In some cases such as instruction set simulation, the target instruction set may be substantially the same as the source instruction set, providing testing and debugging features such as instruction trace, conditional breakpoints and hot spot detection. Dynamic binary translation differs from simple emulation (eliminating the emulator's main read-decode-execute loop, which is a major performance bottleneck), paying instead a one-time large overhead during translation. Any such translation overhead is hopefully amortized as translated code sequences are executed multiple times.
In partial binary translation, the native ISA code is executed when possible and only parts of it are translated and run from the translation cache area. This approach is suitable for translating code from a central processing unit (CPU) of one architecture to a CPU of a similar architecture type where some subset of instructions may not be supported on the target architecture. ISA consistency between similar but different CPU types is important in systems that include heterogeneous high-performance and power-efficient CPUs in order to produce superior performance per power capabilities.
However, ISA consistency among different CPU types is considered a hard problem to solve due to the heavy constraints on manufacturing costs of the hardware and very tight limits on the power consumption and chip areas for CPUs that need to operate in small devices which do not typically include elaborate cooling components. As a result, there is an ISA gap between the lower-end embedded CPUs designed for small low-power devices versus the high-end CPUs designed for desktop computers or servers and include additional ISA features for enhanced computation.
To date, potential solutions to such under utilization, fault tolerance, performance and efficiency limiting issues have not been adequately explored.